Senior Validation Engineer
- Posted 7 hours ago
- Be among the first 10 applicants
Job Description
ACL Digital is hiring a Validation OS Developer / Engineer (4–14 Yrs) in Hyderabad for immediate joiners (0–30 days notice). You will develop validation frameworks, drivers, and test plans while handling C/Data Structures and debugging in both Pre-Silicon and Post-Silicon environments. The 4-round selection process includes a Programming Test, two Technical Rounds, and a Managerial Round. If you have strong root-cause analysis skills and OS-level expertise, apply now by sending your CV to [Confidential Information].
More Info
Key Skills
OS-level expertise
Post-Silicon environments
Validation frameworks
About Company
Skills:
C, Vcs, DDR, Pcie, Verilog, Scripting Languages, Python, Nvme, Perl, Ethernet, Tcl, PCIe Lecroy, Lab equipment, RTL simulation tools, Viavi Exerciser Analyzer, HBM, RTL Coding, LPDDR, Modelsim, Makefiles, IP SOC design methodologies, systemverilog, FPGAs, Axi, AMBA, UNIX Shells, CXL, APB protocol, AHB
Skills:
C, Python, AI-ML based compiler tools, graph optimization techniques, graph programming model
Skills:
C, Nvme, C++, Vcs, Pcie, Verilog, Ethernet, Ddr3, RTL simulation tools, IP SOC design methodologies, systemverilog, Rtl Design, LPDDR3, AMBA, Axi, HBM, CXL, Modelsim, APB protocol, AHB
Skills:
Fpga, Spi, C Programming, Uart, MACSEC, CTLE, DFE, SERDES, JESD204C, MIPI, PCIe Gen4, JESD204B, I3C, USB 3.2, 1588 PTP, NOC Trace