Senior Staff Engineer - AMS Verification

• Ability to lead MSV and/or DV verifications.
• Involved in verification forIPs.
• Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans, Mentoring Junior engineer.
• Test plan preparation as per the dynamics of product specifications.
• Behavioral modeling:Verilog, real or SV-RNM.
• Dealing challenges withAMS methodologiesofCadence:irun/xrunorSynopsys: XA-VCSorMentor Eldo ADMS.
• Testcase Debug & proposing new scenarios.
• Ability to strategize optimization of simulation bench for simulation time.

Your Profile

You are best equipped for this task if you have:

• Bachelors with 9+ years or Masters with 8+ years of experience.
• Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage.
• HDL/HVL:Verilog/Verilog-ams,SV/UVMadded advantage.
• Tools:Cadence Xceliumspectre/Synopsys XA-VCS/Mentor Eldo ADMS.
• Automation: Perl/python/shell.
• Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements.
• Ability to drive projects and debug independently