Senior Staff DFT Engineer

Senior Staff DFT Engineer

Location: Bengaluru

Experience: 12–16 Years

Role Overview

We are looking for a Senior Staff DFT Engineer with deep hands-on expertise in DFT architecture, implementation, ATPG and silicon bring-up for complex SoC designs.

Key Responsibilities

• Own DFT architecture and methodology for complex SoC/full-chip designs.
• Drive Scan insertion, ATPG, MBIST, JTAG and test compression implementation.
• Develop and validate DFT specifications, test modes and coverage targets.
• Drive ATPG pattern generation, coverage analysis and fault debug.
• Analyze and resolve DFT timing, test power, coverage and physical implementation issues.
• Collaborate with RTL, Physical Design, STA, Verification and Silicon teams through tapeout and bring-up.
• Develop DFT flows and automation using Tcl/Python/Perl.

Core Technical Skills

• Strong expertise in Scan, ATPG, MBIST, JTAG, EDT/Test Compression.
• Hands-on experience with Synopsys DFTMAX/TestMAX, TetraMAX or Siemens Tessent.
• Deep understanding of stuck-at, transition, path-delay and memory fault models.
• Strong knowledge of DFT architecture, testability, coverage and test modes.
• Experience with advanced-node SoCs and full-chip DFT signoff.
• Strong scripting, debugging and cross-functional technical leadership.

Ideal Candidate: A deeply hands-on DFT technical leader capable of owning SoC DFT from architecture through implementation, signoff and silicon bring-up.