Senior Sta Engineer

Sykatiya Technologies, founded in 2012, delivers comprehensive VLSI design, test services, and specialized solutions tailored to meet clients project demands. Known for its expertise in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs, the company excels in providing turnkey and bespoke solutions. Sykatiya specializes in disruptive ultra-low power optimization technologies, helping clients meet or surpass power and area targets while ensuring design excellence. With a customer-first philosophy and a talented team, Sykatiya emphasizes technical ability and innovation to drive superior results in the RTL-to-GDS implementation process.

We are seeking a Senior STA (Static Timing Analysis) Engineer for a full-time, on-site role located in Bengaluru South. As a key member of the team, you will be responsible for timing closure and analysis for complex ASIC designs, implementing timing constraints, and developing methodologies for timing sign-off. This role requires close collaboration with cross-functional teams including RTL designers, physical design, and design for test (DFT) engineers. You will also support debugging and validation efforts while continuously improving workflows and tools to enhance efficiency and quality.

• Expertise in Static Timing Analysis (STA) tools and methodologies, along with timing closure at chip and block levels
• Proficiency in scripting (Tcl, Perl, Python, or similar) for automating design workflows and improving efficiency
• Strong understanding of timing scenarios, dynamic voltage scaling, and ultra-low power design techniques
• Experience in various EDA tools, including PrimeTime, Tempus, or similar tools
• Solid knowledge of physical design processes such as place and route, RC extraction, and clock tree synthesis
• Bachelor's or Master's degree in Electrical, Electronics, or comparable engineering fields
• Excellent problem-solving skills, teamwork abilities, and communication expertise
• Prior experience in ultra-low power optimization and RTL-to-GDS flow is highly advantageous