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Senior STA Engineer

Nxp Semiconductors
Bengaluru, India
4-7 Years
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Job Description

Summary: The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC design.

Job Qualification

  • Experience range: 4-7 years
  • Should be good in Synthesis Flow setup and Synthesis flows. Should have worked on Genus flows.
  • Should be good in STA flow setup and STA flows. Should have worked in Tempus flows.
  • Should have worked on STA timing ECOs across multiple technology nodes.
  • Should have good understanding in Constraints , clocks.
  • Should have excellent communication skills and should be team player.

Job Responsibilities

  • The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC design.
  • The individual is responsible from RTL synthesis setup , flow cleanup , run multiple experiments to get the best Area , timing and Power , Post-Scan Synthesis netlist STA timing checks , LEC flow setup and cleanup , timing convergence (STA) including related design and timing ECO and should be able to understand the constraints and suggest constraints to Design/DFT teams .
  • The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.

More information about NXP in India...

More Info

Job Type:
Permanent Job
Industry:
Semiconductor Manufacturing
Function:
Engineering
Employment Type:
Full time

About Company

Nxp Semiconductors

Job ID: 149385949

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Last Updated: 21-06-2026 08:45:11 PM
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power optimization , python, perl, Routing, Tcl, CTS, Signoff checks, Timing ECOs, Timing Analysis and Closure, EM, DFT insertion, IR flows, Scan DFT modes, RTL to GDS, Physical Verification, Extraction, Placement, Timing Constraints Development, Check Timing Analysis, Floor-planning, Digital Synthesis, Check Design