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Senior/Principal verification Engineer

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Job Description

Verification Planning & Execution

  • Define comprehensive verification strategies and verification plans based on architecture and design specifications.
  • Develop and execute block-level, subsystem-level, and SoC-level verification environments.
  • Drive verification closure through functional, code, assertion, and toggle coverage metrics.
  • Create test plans, verification testcases, and sign-off criteria.

Testbench Development

  • Architect and develop scalable SystemVerilog/UVM-based verification environments.
  • Design reusable Verification Components (UVCs), scoreboards, checkers, monitors, and reference models.
  • Develop constrained-random, directed, and scenario-based tests.
  • Integrate third-party VIPs and custom verification IPs.

Assertion & Formal Verification

  • Develop SystemVerilog Assertions (SVA) for protocol and functional checking.
  • Utilize assertion-based verification techniques to improve bug detection efficiency.
  • Collaborate with formal verification teams for property development and closure.

Debug & Root Cause Analysis

  • Analyze simulation failures and identify RTL, testbench, or architectural issues.
  • Work closely with design and architecture teams to resolve functional and performance-related bugs.
  • Lead complex debug activities across multiple IPs and subsystems.

Coverage & Sign-Off

  • Define and track functional coverage models.
  • Drive functional, code, assertion, and cross-coverage closure.
  • Review verification metrics and provide sign-off recommendations.
  • Ensure compliance with overall project verification and quality goals.

SoC Verification

  • Lead end-to-end verification of large SoCs including:
    • Interconnect and fabric verification
    • Cache coherency verification
    • Memory subsystem verification
    • Boot and reset validation
    • Low-power verification
    • Performance and stress testing
Leadership & Mentoring

  • Provide technical leadership to verification teams.
  • Mentor junior and senior engineers on UVM, verification methodologies, and debug techniques.
  • Participate in hiring, technical interviews, and project planning.
  • Drive best practices and verification process improvements.

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About Company

Job ID: 153618977

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