Senior/Principal ASIC Design Verification Engineer (SoC/Subsystem)

Proxelera is hiring genius who will be working with us for cutting edge projects

Role:

Own complete RTL design for complex SoC or major subsystem blocksfrom microarchitecture to tape out and silicon bringup.

Responsibilities:

• Define microarchitecture and develop highquality synthesizable System Verilog/Verilog RTL.
• Lead design bringsup, integration, and close timing/power/area with synthesis and PnR teams.
• Run design reviews, fix bugs, and support silicon validation and postsilicon debug.

MustHave:

• 8+ years handson ASIC RTL design (FPGA not counted).
• Multiple production ASIC tape outs owning major SoC/subsystem functions.
• Strong RTL Coding/microarchitecture skills, lowpower design.

Job Location: Bangalore (WFO)