Senior Physical Design & STA Lead

Company Description

AI Chips specializes in developing custom chip solutions to accelerate Machine Learning (ML) for practical, real-world applications. Our advanced ASIC and FPGA solutions are designed to meet the industry's demand for devices with lower Size, Weight, Power, and Cost (SWaP-C) compared to traditional CPU and GPU designs. AI Chips is at the forefront of innovation, providing tailored silicon solutions that meet high-performance needs while maximizing efficiency and cost-effectiveness. We are passionate about redefining possibilities in AI hardware technology.

Role Description

AI Chips is seeking a hands-on Senior Physical Design & STA Lead with 10–15 years of experience and a strong track record of 10–15 tape outs to join our team in a full-time capacity. This on-site role, based in Hyderabad, India, involves leading a small team to execute physical implementation and Static Timing Analysis (STA) across various projects, with an emphasis on AI silicon. The role includes floorplanning, timing closure, place and route (PnR), and collaborating with cross-functional teams to deliver high-quality solutions that meet critical schedules. The ideal candidate will be actively involved in design execution while mentoring junior team members and driving technical excellence.

We're building a next‑generation AI accelerator and need a hands‑on Senior Physical Design & STA Lead who has driven 10–15 successful tapeouts and still enjoys being directly in the tools every day. This is not a supervisory or oversight‑only role — you will personally own and execute major blocks, top‑level integration, and timing closure while also guiding a small team.

If you want to architect the backend flow and be the engineer who actually pushes the design to closure, this role is built for you.

Key Skills and Responsibilities

·       Perform full physical design implementation: synthesis, floorplanning, power planning, placement, CTS, routing, extraction, ECOs, and signoff.

·       Run and own STA directly: MCMM analysis, derates, OCV/AOCV/POCV, constraint development, and timing closure.

·       Execute top‑level integration: build block abstracts, define timing budgets, run top‑level STA, and close chip‑level timing yourself.

·       Drive PPA optimization hands‑on: identify critical paths, perform placement/clocking optimizations, and propose RTL fixes.

·       Perform IR/EM analysis: run static/dynamic IR drop, EM checks, and implement mitigation strategies.

·       Run physical verification: DRC, LVS, ERC, antenna, density, and foundry signoff.

·       Execute late‑stage ECOs: functional, timing, and physical ECOs across the final closure window.

·       Develop automation: write Tcl/Python scripts to improve timing analysis, PPA reporting, and signoff flows.

·       Collaborate tightly with RTL, architecture, and verification to drive timing‑aware design decisions.

Leadership Responsibilities (But Still Hands‑On)

·       Mentor junior and mid‑level PD/STA engineers through reviews, methodology guidance, and example‑driven leadership.

·       Define physical design methodology and best practices, but also demonstrate them through your own implementation work.

·       Help scale the backend team while remaining an active contributor to block‑ and top‑level closure.

Job Roles and Responsibilities

·       10–15 years of physical design and STA experience with 10–15 successful tapeouts

·       Location: Hyderabad, India

·       Qualifications: B.Tech, M.Tech, Ph. D., in Electrical Engineering, Computer Engineering, or related field

·       Deep, hands‑on expertise with: (1) STA: PrimeTime or Tempus; (2) P&R: Innovus, ICC2, or Fusion Compiler; (3) Synthesis: Genus or Design Compiler; (4) Physical verification: Calibre or Pegasus

·       Proven ability to personally close timing on complex, high‑frequency designs

·       Strong understanding of: Clocking (mesh, H‑tree, multi‑source CTS), Power grid design, IR/EM analysis, Advanced‑node physical effects (variation, SI, RC extraction)

·       Strong scripting skills (Tcl, Python, Shell)

·       Experience with AI/ML accelerators, GPUs, DSPs, or high‑performance compute is a plus.

·       Ability to work in a fast‑moving, high‑ownership startup environment.

·       Experience in collaborating with engineering teams

·       Strong analytical and problem-solving skills

·       Excellent communication and teamwork skills

Why This Role Matters

·       You are the engineer who ensures the chip meets frequency, power, and area targets.

·       You directly drive timing closure, IR/EM integrity, and signoff quality.

·       Your hands‑on execution determines whether the chip tapes out on schedule.

Why Join Us

·       Architect and execute the backend flow for a ground‑up AI accelerator.

·       Own top‑level physical design and STA with real autonomy.

·       Work with a small, elite team where your contributions directly shape the silicon.

·       High impact, high ownership, and early‑stage equity.