Senior Physical Design Engineer

Full Chip Physical Design Engineer

Location: Bengaluru, India

Experience: 5–12 Years

About the Role

We are looking for a Full Chip Physical Design Engineer to drive the implementation and signoff of complex, high-performance SoCs across advanced technology nodes. You will own full-chip physical design convergence, collaborating with Architecture, RTL, Synthesis, DFT, and Signoff teams to deliver first-pass silicon.

Key Responsibilities

• Drive end-to-end Full Chip Physical Design from netlist handoff through final GDS signoff.
• Own full-chip integration, floorplan validation, partitioning, and implementation convergence.
• Perform Static Timing Analysis (STA) and drive MCMM timing closure across all functional and test modes.
• Analyze and resolve timing violations using ECO implementation, logic optimization, buffering, cell sizing, and useful skew.
• Perform EM/IR analysis, power integrity validation, and collaborate on IR/EM closure.
• Drive synthesis QoR optimization and work closely with RTL teams on timing-aware design improvements.
• Collaborate with CTS, Routing, DFT, Physical Verification, and Package teams to achieve design closure.
• Develop automation scripts and improve implementation methodologies for advanced-node designs.

Required Qualifications

• 5–12 years of hands-on experience in Full Chip Physical Design.
• Strong expertise in Static Timing Analysis (STA), MCMM timing closure, and timing signoff.
• Solid experience in EM/IR analysis, ECO timing closure, and RTL-to-GDS implementation.
• Strong knowledge of Synthesis, SDC constraints, CTS, Routing, and Physical Design methodologies.
• Hands-on experience with Synopsys ICC2/Fusion Compiler, PrimeTime, Design Compiler, and RedHawk/Voltus or equivalent tools.
• Experience with advanced technology nodes (7nm/5nm/3nm) is highly preferred.
• Proficiency in Tcl, Perl, or Python scripting for flow automation.

Preferred Qualifications

• Experience with hierarchical/full-chip integration, Low-Power (UPF), and advanced packaging (2.5D/3DIC).
• Strong understanding of DFT-aware implementation and signoff methodologies.
• Excellent debugging, analytical, and cross-functional collaboration skills.