Job description

 About The Role  Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

 Qualifications Minimum QualificationsGraduate of Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with at least 6+ years experience in the following:Micro-architecture and RTL design for advanced SoCsExpertise in link and network layers of coherent fabric systemsHands-on experience in developing protocol bridges for interface translations; and experience with coherent protocols (CXL, CCIX, PCIe, or similar) and interconnect technologies OR;Graduate of Master's Degree in Electrical Engineering, Computer Engineering, or a related field with at least 4+ years experience in the followingMicro-architecture and RTL design for advanced SoCsExpertise in link and network layers of coherent fabric systemsHands-on experience in developing protocol bridges for interface translations; and experience with coherent protocols (CXL, CCIX, PCIe, or similar) and interconnect technologies OR;PhD in Electrical Engineering, Computer Engineering, or a related field.Technical Experience- Proficiency in RTL design using Verilog or SystemVerilog.- Knowledge in micro-architecture and pipeline design.- Expertise in simulation, debugging, and performance tuning tools.- Knowledge in scripting languages (Python, Perl, or TCL) for automation and design flow optimization.