Senior Memory Layout Engineer
Experience-(4–8 Years)
Location: Hyderabad
About the Role
Join a world-class silicon engineering team developing next-generation SRAM and memory IP for advanced SoCs. As a Senior Memory Layout Engineer, you will own the physical implementation of high-density memory macros, working closely with circuit design and process teams to deliver silicon-proven, high-performance memory solutions.
Key Responsibilities
- Develop full-custom layouts for SRAM and memory macros, including bitcell arrays and peripheral circuits.
- Design layouts for Sense Amplifiers, Write Drivers, Row/Column Decoders, Precharge Circuits, Redundancy Logic, and Control Blocks.
- Ensure layouts meet DRC, LVS, ERC, antenna, density, and EM requirements.
- Perform parasitic-aware layout optimization for performance, power, area, yield, and manufacturability.
- Collaborate with circuit design teams on floorplanning, matching, routing, shielding, and layout optimization.
- Support post-layout verification, extraction, silicon debug, and yield improvement activities.
Required Qualifications
- B.E./B.Tech/M.E./M.Tech in Electronics or related discipline.
- 4–8 years of hands-on experience in Memory Layout or Custom Layout engineering.
- Strong expertise in SRAM layout, bitcell arrays, memory periphery, matching techniques, and custom physical design.
- Proficiency with Cadence Virtuoso Layout XL, Calibre DRC/LVS, and parasitic extraction tools.
- Solid understanding of advanced process nodes, design rules, layout-dependent effects (LDE), and reliability considerations.
Preferred Experience
- Experience with FinFET technology nodes and advanced semiconductor processes.
- Exposure to high-performance CPU, GPU, AI Accelerator, or Networking SoCs.
- Knowledge of automation using SKILL, Python, Perl, or TCL is an advantage.
What You'll Bring
- Strong attention to layout quality and physical design excellence.
- Ability to solve complex layout challenges with a focus on first-pass silicon success.
- Excellent collaboration skills and a high level of ownership in a fast-paced engineering environment.
