Job Title: Design & Verification Engineer
Location: Noida
Looking for Siemens EDA ambassadors:
Verifications of internally developed VTL (Veloce friendly standard protocols eg. AMBA, PCIe, SAS, Ethernet, MIPI etc) using standard verification methodologies including UVM and signoff based on coverage matrix.
Job Description -
- Development of verification environments using standard verification methodologies on standard protocol like PCIe/SAS/SATA etc
- Verification at IP level to ensure 100% Functional and Code Coverage
- Suggest and prototype various verifications flows using Veloce
- Integration and qualification of various VTLs with Questa Based Verification IPs using
- Customer use model within internal test suites
- May requires interfaces with customers and travel to customer sites
- Development of methodology suites and automating the same
Skill Sets Required:
Protocol / Practical experience on any of the following protocol is necessary –
- AMBA
- PCI/PCIe
- SAS
- Ethernet
- MIPI
- B.Tech/M.Tech in ECE, EE, VLSI with 2-5 years of experience
- Experience in IP and SOC level verification
- Knowledge of verification methodologies like Specman, SV,UVM, OVM, TLM, Assertion, Coverage, co-simulation, co-verification
- Good communication skills as person needs to work with external interfaces
- FPGA/Emulation experience is high positive
- Good scripting and automation knowledge is big plus for the role
Education
- Graduate / Post Graduate (Bachelors/Masters) in Computer Science / Electronics & Electronics (EEE) / Electronics & Communication Engineering (ECE).
#Onsite
