Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
- As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems.
- Design and architect different interconnect topologies as driven by bandwidth, latency, and RAS requirements
- Develop the features, present the proposed architecture in the High level design discussion
- Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature
- Signoff the Pre-silicon Design that meets all the functional, area and timing goals
- Participate in silicon bring-up and validation of
the hardware
Required Technical And Professional Expertise
- 8 to 15 years of relevant experience
- At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC).
- Experience in different on-chip interconnect topologies (e.g., mesh, crossbar)
- Understanding of various snoop and data network protocols
- Understanding of latency & bandwidth requirements and effective means of implementation
- Working knowledge of NUMA/NUCA architecture
- Proficient in HDLs- VHDL / Verilog
- Experience in High speed and Power efficient logic design
- Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage
- Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design
- Experience in leading uarch, RTL design teams for feature enhancements.
- Follow agile project leadership principles. Work with the team on estimation and execution plan
