Senior Lead Engineer - DV
Senior Lead Engineer - DV
Quest Global5-7 Years
- Posted 3 hours ago
- Be among the first 10 applicants
Job Description
Job Requirements
At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
Extensive experience in SV/UVM based SOC or IP Verification.
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
Work Experience
Required Skills
Health Insurance, Medical Benefits, Annual Leave
At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
- Job Summary:
Extensive experience in SV/UVM based SOC or IP Verification.
- Key Responsibilities:
- Own and delivery IP/Subsystem/SOC Testbench development, define Test plan, Test development & debug.
- Strong knowledge in CPU based SOC architecture.
- Develop and execute System Verilog/UVM Testbenches for SOC/IP Verification
- Develop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random tests
- Analyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution.
- Define Functional/Code/Assertion coverage metrics, sign-off checklist and drive to closure.
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
Work Experience
Required Skills
- 5+ years of hands-on experience in IP/SOC Verification with Strong SOC Architecture knowledge
- Proficiency in SV/UVM based testbench development and constrain random verification.
- Familiarity with standard verification tools ( VCS, Xcelium) and debug environment
- Scripting skills ( Python/Perl)
- Strong debugging, analytical and problem-solving skills
- Experience in two or more High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)
Health Insurance, Medical Benefits, Annual Leave
