Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.

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Our company is built by dedicated team players who love to challenge the status quo we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

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Job Description:

.Execute FPGA/EDA Software flow testing, i.e. validating the correctness of IDE Flows (Design generation, synthesis, place-and-route, timing analysis, and bitstream generation flows).

.Create and maintain TCL-based test cases for automating EDA tool flow validation.

.Develop and review test plans for new features or EDA flow enhancements, ensuring comprehensive coverage of use cases.

.Perform regression analysis by executing automated test suites, debugging failures, and tracking issues to closure.

.Design and develop Verilog/System Verilog test benches to verify FPGA macros and configurators.

.Perform pre-synthesis functional simulations to validate correctness and compliance with requirements.

.Analyze and interpret simulation waveforms, debug issues, and report bugs to development team in Jira system.

.Develop Python scripts to automate repetitive tasks such as log parsing, regression execution, coverage analysis, and report generation.

.Work closely with senior engineers to understand FPGA design flow (synthesis, place and route and Timing analysis).

Requirements/Qualifications:

.Strong knowledge of Verilog HDL for verification.

.Hands-on experience with simulation tools (e.g., ModelSim, Questa, VCS) for pre-synthesis functional verification.

.Proficiency in analyzing waveforms and debugging simulation mismatches.

.Understanding of digital logic design fundamentals: combinational/sequential logic, FSMs.

.Familiarity with TCL and Python scripting for automation of EDA workflows (log analysis, regression automation, etc.).

.Exposure to test planning, regression analysis, and bug tracking processes.

.Exposure to synthesis concepts and awareness of RTL coding styles for synthesis-friendly design.

.Good problem-solving skills and ability to work in a collaborative team environment.

.Strong communication and documentation skills.