Senior Engineer DV
- Posted 6 days ago
- Be among the first 10 applicants
Job Description
Job Requirements
- Verification Planning and Test Development
- Review design specifications and requirements to develop comprehensive verification plans
- Design and implement test benches and test vectors to simulate system behavior
- Develop coverage-driven, reusable, and portable verification environments at IP, subsystem, or SoC levels
- Simulation and Debugging
- Execute verification tests using simulation tools such as ModelSim, VCS.
- Analyze test results, identify bugs, perform root cause analysis, and propose solutions
- Apply formal verification methodologies when applicable to ensure design correctness
- Collaboration and Communication
- Work closely with design engineers, architects, and system engineers to address design-related concerns
- Participate in design reviews and provide insights to improve system performance
- Document verification processes, test plans, and results for team reference and compliance.
- Tools and Methodologies
- Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog, or VHDL
- Familiarity with scripting languages like Python, Perl, or TCL for automation
- Knowledge of Universal Verification Methodology (UVM) for building reusable test environments
More Info
About Company
Skills:
System Verilog, Performance Verification, AMBA Based bus knowledge, Ace, Safety and Security verification, CPU SS Verification, Interconnect Verification, Uvm, Axi, formal verification, Automotive SoC DV expertise, SoC level verification, Low Power Verification, AHB, System Verilog Assertions
Skills:
Verilog, random stimulus, assertion-based verification, Uvm, bus functional models, functional coverage, scoreboards, checkers, advanced verification methodologies, VMM, systemverilog, monitors