Senior Embedded Test Engineer (Fibre Channel/PCIe)

Senior Embedded Test Engineer (Fibre Channel/PCIe)

Role Overview:

Lead the validation and optimization of next-generation Fibre Channel HBAs. Ensure data integrity and performance from PCIe to Fibre Channel PHY across multi-core proprietary RISC processors. Write highly optimized Assembly and C code for real-time, memory-constrained stress testing.

Key Responsibilities:

Architect & design test suites for end-to-end IO data paths (PCIe host to FC engines/RISC clusters to FC PHYs).

Write and maintain optimized RISC Assembly and C for benchmarking and hardware verification.

Develop test firmware for memory-constrained, real-time embedded platforms to identify critical issues (race conditions, memory leaks).

Validate data coherency and synchronization across multi-RISC systems for high-availability storage performance.

Root-cause complex firmware/hardware issues using JTAG, PCIe/FC protocol analyzers.

Required Technical Skills:

Good knowledge of RISC architecture, ability to write/debug manual Assembly and C.

Proficiency in creating automated, high I/O load test environments to ensure data integrity.

Extensive experience in memory-constrained, real-time environments.

Demonstrated ability to validate data flow and synchronization in multi-processor/parallel processing systems.

Experience with PCIe (Gen 4/5/6) and/or Fibre Channel.

Preferred Qualifications:

FC/NVMe-oF experience, ASIC/FPGA validation, strong understanding of DMA and interrupt handling in high-speed networking.