Senior Design Verification Engineer

Company Description

KriSemi Design Technologies is a premier service provider in the semiconductor industry, specializing in Physical Design, Physical Verification, Analog and Mixed Signal Design, Embedded Systems, and software solutions. Our team comprises experienced professionals with deep expertise in addressing complex VLSI challenges and a strong focus on future-facing technologies. Guided by a culture of pride and passion, KriSemi is committed to delivering high-quality technology solutions that help clients meet their business objectives. Headquartered in Hyderabad, we collaborate with leading semiconductor companies worldwide, consistently expanding our impact and expertise.

Job Description: DDR Verification Engineer

Role Overview

Will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.

Technical Skills - 510 years experience in SoC or IP-level verification (memory subsystems preferred).

1. Strong knowledge of DDR protocol (JEDEC specifications).
2. Experience with SystemVerilog, UVM, and verification methodology.
3. Hands-on with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
4. Good understanding of memory controller architecture and timing parameters (setup/hold, tRCD, tRP, etc.).
5. Knowledge of AXI protocol and its integration with DDR controller.
6. Familiarity with assertions (SVA), scoreboarding, and functional coverage.
7. Familiarity with GLS is a plus.

Key Responsibilities

1. Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
2. Define verification plans, design testbenches, and create directed and constrained-random testcases.
3. Write and debug testcases and sequences for DDR protocol features (read/write operations, refresh, training, power-down modes).
4. Validate ECC, parity, and command/address/data integrity mechanisms.
5. Develop and debug scoreboards, assertions (SVA), and checkers for data integrity and protocol correctness.
6. Integrate AXI, APB VIPs with DDR subsystem.
7. Perform coverage analysis (code, functional, assertion) to ensure verification completeness.
8. Debug RTL and simulation failures using waveform analysis (SimVision, Verdi).
9. Work with design teams to debug RTL and root-cause functional/timing issues in RTL and GLS.
10. Collaborate with post-silicon and firmware teams for memory bring-up and validation.

Education/Experience

1. B.E/B.Techor M.E/M.Techin Electronics, Electrical, or Computer Engineering.
2. 510 years experience in SoC or IP-level verification (memory subsystems preferred).

Soft Skills

1. Strong analytical and debugging skills.
2. Able to deliver tasks independently.
3. Good documentation and communication ability.
4. Comfortable collaborating across design, validation, and firmware teams.