Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft LabsEarly Applicant
- Posted a month ago
- Be among the first 10 applicants
Job Description
Hi All,
ACL Digital is looking for Senior Design Verification Engineers
Exp Level: 4+ years
Notice period: Immediate to 30 days
Location: Bangalore and Hyderabad
Job Description:
- Must have good knowledge on the verification flows
- Excellent hands-on debug skills and problem solving attitude.
- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC.
- Experience of working on Functional Verification, SoC Verification, Emulation
- Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language
- OVM/UVM Methodology knowledge and experience
- Must have good communication skills and the ability to work in a team environment.
- Preferably having experience in architecture such as x86 or ARM domain based SOCs
- having SOC/IP performance verification background is added plus.
Interested can share CV to [Confidential Information]
About Company
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
www.acldigital.com
More Info
Key Skills
System Verilog PLI
DPI interface
About Company
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
Design Verification, Debugging RTL Verilog designs
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog