Senior Design Verification Engineer

GLS Verification Lead Engineer

Experience : 8+ years

Location : Bangalore

We are looking for someone to strengthen the ASIC Top level team with respect to GLS.

We are currently developing two main dies to be instantiated in various configurations in different ASICs.

One die consists of a huge number of DSPs and even more accelerator IPs for different type of computing. The same die also a common memory used by all DSPs and accelerators IPs.

Role in the Team

When working with GLS you will be involved in

• Tailor the SystemVerilog/UVM testbench to support GLS
• Verify power-up and reset sequence
• System initialization
• Verifying DFX structures added after synthesis.
• Verify all interfaces that are used for the silicon bring-up

Skills you bring

Skills you must possess:

• Experience of GLS of large ASIC designs, zero delay as well as with annotated SDF.
• Experience X-propagation debug.
• Solid RTL and netlist debugging skills in SystemVerilog or VHDL designs.
• C-programming experience, to be able to modify tests if necessary
• Understanding of how to reduce long simulation time of very large ASIC designs. This e.g. requires an understanding of how to user grey box/black box concept from IP level to chiplet level.
• Understand what to initialize and when, to get the GLS working.
• Experienced with Verdi on large designs.

Other desired knowledge and experience:

• Experience with git, Gerrit and Jenkins.
• Some experiences from external interfaces is a plus

Interested,please drop your updated resume to [Confidential Information]