Senior Design Verification Engineer - 5+ yrs only

HCLTech is looking for a Senior Design Verification Engineer with strong experience in high-speed interfaces such as DDR,UCIe, PCIe, CXL, Ethernet, and NVMe.

Location: Bangalore, Chennai, Hyderabad

Experience: 514 years

Interested Send your resume to: [Confidential Information]

Responsibilities:

Develop test plans and verification infrastructure for complex IPs, subsystems, and SoCs.

Build UVM-based verification environments.

Create reusable BFMs, monitors, checkers, and scoreboards.

Drive functional coverage and verification closure.

Collaborate with architects, designers, and DFT teams.

Skill Set:

BTech/MTech with 4 7years of relevant experience.

Strong in System Verilog and UVM.

Experience in IP/Sub-system/SoC level verification.

Familiar with code coverage, functional coverage, and assertions.

Hands-on with:

UCIe or PCIe

Bus protocols: AXI, AHB, APB

Industry-standard simulation and debug tools

Excellent debugging and communication skills.

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