Senior and Lead Analog Layout Engineer

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company delivering end-to-end chip solutions for global customers. The company offers strong capabilities across the full semiconductor design spectrum, including analog circuit design, custom layout, physical design, verification, and embedded design. SiMaxTech works on a wide range of technology nodes from mature nodes like 65nm and above to advanced nodes such as 7nm, 5nm, 3nm, while scaling toward cutting-edge nodes like 2nm and 18A. Guided by a vision to be the preferred semiconductor design partner worldwide, the team focuses on continuous learning, innovation, and execution excellence. With a customer-centric approach, SiMaxTech is known for high-quality design solutions, performance, reliability, and scalability.

We're hiring for Analog Layout Engineers

Experience: 4 to 10 Years

Location : Bangalore

Notice Period : Immediate to 30 Days

Role Description This is a full-time, on-site role for Senior and Lead Analog Layout Engineers based in Bengaluru South. The role involves ownership of custom analog and mixed-signal layout design for complex blocks and sub-systems, including planning, floorplanning, device placement, routing, and optimization for performance, area, and manufacturability. Daily responsibilities include collaborating closely with circuit designers to understand specifications, translating schematics into robust layouts, and performing iterative refinement to meet matching, noise, IR drop, and electromigration requirements. The engineer will drive physical verification sign-off (DRC, LVS, ERC, density checks), resolve verification issues, and ensure layouts comply with foundry design rules across multiple process nodes. Senior and Lead engineers are expected to mentor junior team members, contribute to layout methodologies and automation, participate in design reviews, and coordinate with cross-functional teams to meet project schedules and quality targets.

Qualifications

• Strong foundation in analog and analog circuits, with the ability to interpret complex schematics and design intent.
• Proficiency in layout design for analog and mixed-signal blocks, including matching-critical structures and high-voltage or RF-sensitive layouts.
• Experience in circuit design collaboration, working closely with designers to optimize performance, reliability, and yield.
• Hands-on expertise in physical verification, including DRC, LVS, ERC, and sign-off flows across multiple process technologies.
• Practical knowledge of industry-standard EDA tools for custom layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys) and familiarity with foundry PDKs.
• Experience across advanced and mature technology nodes; exposure to FinFET processes is an advantage.
• Ability to lead projects, mentor engineers, and contribute to layout methodologies, scripts, and best practices.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field, with relevant experience