Senior Analog layout Engineer

Experience: 8–10 Years (flexible for the right candidate)

Key Requirements

*Hands-on experience in from 130nm to 22nm is a must.

*Experience with Intel, Samsung, GF, or other leading foundries is good to have.

*TSMC 16nm/5nm/3nm experience is also good to have.

*Strong experience in critical analog, mixed-signal, and custom digital block layout, including full-chip integration support.

*experience with analog blocks such as regulators, charge pumps, power management blocks, etc.

*Expertise in LVS, DRC, DFM, Antenna, and EM/IR verification flows.Proven ability to deliver high-quality block-level layouts on schedule.

*Cadence Virtuoso VLE/VXL and Mentor Graphics Calibre DRC/LVS experience is a must.

*Ability to work independently and take ownership of layout deliverables, and lead a small team.

*Strong communication skills and ability to collaborate with cross-functional teams.