SCAN DFT, ATPG, Diagnostic, Coverage Analysis
SCAN DFT, ATPG, Diagnostic, Coverage Analysis
Randstad Sourceright8-15 Years
- Posted 10 hours ago
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Job Description
Position: SCAN DFT, ATPG, Diagnostic, Coverage Analysis (BB612FT RM 4438)
Job Responsibilities
The DFT Engineer is responsible for Hardware Design-For-Test (DFT) activities for high-performance chip designs to enable efficient high-coverage Test. This includes scan-based logic test, memory test and repair, boundary scan, and high-speed interface testing. The engineer will develop appropriate DFT methodology and flows, and work with the front-end design team to integrate and flush new DFT features & methodologies into the design and document the DFT architecture. The engineer will work on Industry-standard tools for DFT implementation, Pattern generation, Simulation and verification of the DFT features. The engineer will interface with the back-end team on timing, physical design and with the PDTE team on ATE pattern delivery & ATE silicon bring up.
Requirements
Job Responsibilities
The DFT Engineer is responsible for Hardware Design-For-Test (DFT) activities for high-performance chip designs to enable efficient high-coverage Test. This includes scan-based logic test, memory test and repair, boundary scan, and high-speed interface testing. The engineer will develop appropriate DFT methodology and flows, and work with the front-end design team to integrate and flush new DFT features & methodologies into the design and document the DFT architecture. The engineer will work on Industry-standard tools for DFT implementation, Pattern generation, Simulation and verification of the DFT features. The engineer will interface with the back-end team on timing, physical design and with the PDTE team on ATE pattern delivery & ATE silicon bring up.
Requirements
- Bachelor's/Master's degree in Electrical Engineering or equivalent practical experience 8-15 years of experience in DFT/DFD flows and methodologies.
- Experience with DFT/DFD/DFM technique.
- Well-versed in scan insertion, ATPG, MBIST, JTAG, Scan Compression and at-speed test.
- Strong fundamental knowledge of various Test standards (IEEE 1149.10, 1149.6, 1500, 1687) and test formats (BSDL, ICL, PDL, STIL, CTL)
- Extensive experience with industry standard simulation, ATPG and MBIST tools
- Knowledge of defect types, fault models and low power design methodologies
- Knowledge of timing constraints and STA for test modes
- Experience in DFT related verification and GLS,, SDF simulations
- Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues
- Experience in DFT pattern delivery, silicon bring-up, debug and validation fo DFT features on ATE.
- Experience with scripting languages like Python, Perl, skill, tcl or equivalent to automate flows is a plus.
- Willingness to learn new skills and apply new technologies.
- Strong communication skills and the ability to collaborate in a global team is essential.
- Self-motivated, ability to work independently and excel in a team environment
More Info
Key Skills
About Company
DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ yearsCisco DevNet
Skills:
boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures
DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ yearsCISCO Credit
Skills:
boundary scan , Vcs, Tcl, System Verilog, Python, Perl, Tessent tool sets, TestMax, Logic Equivalency checking, EDA Tools, ATPG, Scan and BIST architectures, primetime, Gate level simulation debugging, Jtag protocols, memory BIST, TetraMax
Skills:
boundary scan , scan compression, pre-silicon design, silicon debug, Scan Insertion, post-silicon debug, production qualification, memory BIST
Skills:
Vcs, System Verilog, ATE patterns, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures, Gate level simulation debugging