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Job Description
RTL Lead
Experience - 8–12 years
Job Location - Bangalore
Responsibilities
Lead RTL design for SoC/IP
Micro-architecture definition
Code reviews and quality checks
Interface with DV, DFT, and PD teams
Skills Requried
Verilog/SystemVerilog
SoC architecture
Low-power design concepts
Experience - 8–12 years
Job Location - Bangalore
Responsibilities
Lead RTL design for SoC/IP
Micro-architecture definition
Code reviews and quality checks
Interface with DV, DFT, and PD teams
Skills Requried
Verilog/SystemVerilog
SoC architecture
Low-power design concepts
More Info
Key Skills
About Company
Skills:
data link layer , PCIe PHY-MAC interface protocols, Physical Layer, flow control, CDC synchronizers, SerDes PHY, async FIFO, integrating PCIe hard IP controller, PnR constraints, CXL 1.1 2.0 or 3.0 protocol knowledge, reset sequencing, Transaction Layer, multi-clock-domain design, wrapper RTL, error handling, SystemVerilog RTL, clock crossing, PCIe power management, PCI-SIG certification process, PCIe architecture, Virtual Channels, PCIe compliance testing, TLP structure
Skills:
low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks
Skills:
Verilog, System Verilog, ASIC SoC design environments, Low-power design techniques, Simulation and debugging tools, Synthesis timing closure
Skills:
Verilog, Perforce, Git, Clock reset domain design, SoC integration, systemverilog, Design Compiler, RDC tools, UPF, spyglass, Axi, APB, BUS Protocols, Genus, Questa, Lint tools, Synthesis awareness, CPF, AHB, Low-power design
Skills:
Timing Closure, Synthesis, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks, low power design, Verilog RTL development, Front-end EDA tools