RTL Integration Engineer PCIe Gen5 to Gen8

Position: RTL Integration Engineer – PCIe Gen5 to Gen8 (BB812FI RM 4549)

Key skills: PCIe Gen5+ controller and PHY integration, PCIe protocol layers (TL/DL/PHY), LTSSM, TLP/DLLP, flow control, replay, PIPE interface, multi-clock design, CDC, reset sequencing, and AXI/APB-based SoC integration.

Must have silicon-proven PCIe Gen5+ experience; exposure to PCIe Gen6 FLIT-mode architecture is strongly preferred.

Preferred exposure: Chiplet/multi-die SoCs, CXL 2.x/3.x, retimer/redriver integration, post-silicon debug and bring-up, ASPM/low-power integration, RAS/AER, and IDE/link-level security.

Role Overview

We are looking for a highly experienced RTL IntegraƟon Engineer to lead PCIe Gen5 and beyond (Gen6/Gen7/Gen8) controller and PHY integraƟon for advanced SoC and chiplet-based designs. The role requires deep PCIe protocol knowledge, strong RTL/SoC integraƟon experƟse, and hands-on experience taking designs from integraƟon through silicon bring-up readiness.

Key Responsibilities

• Integrate PCIe Gen5+ controllers and PHYs into complex SoC architectures
• Own end-to-end RTL integraƟon, including parameterizaƟon, clocking, reset, and CSR integraƟon
• Ensure correct implementaƟon of PCIe protocol layers (TL/DL/PHY) and LTSSM behavior
• Manage speed and width change, recovery, and reset scenarios across generaƟons
• Drive PIPE (4.x / 5.x) PHY interface integraƟon, including power-state and latency alignment
• Implement robust error handling, replay logic support, and AER reporƟng paths
• OpƟmize performance, latency, and power across mulƟple VCs and traffic classes
• Collaborate with DV, PHY, firmware, and soŌware teams to ensure compliance and bring-up readiness
• Support debug and silicon bring-up through visibility hooks and instrumentaƟon
  
  

Required Technical Skills

• Strong hands-on experience with PCIe Gen5 and above RTL integraƟon
• Deep understanding of PCIe architecture (Root Complex, Endpoint, Switch)
• ExperƟse in LTSSM states, transiƟons, and recovery mechanisms
• Solid knowledge of TLP/DLLP formats, flow control, replay, and ordering rules
• Experience with PIPE interfaces and PHY interacƟon (rate/width change, power states)
• Proven skills in mulƟ-clock design, CDC, and reset sequencing
• Familiarity with ASPM (L0s, L1, L1.1, L1.2) and low-power integraƟon
• Strong understanding of error handling, RAS, and AER capability integraƟon
• Experience integraƟng PCIe into AXI/APB-based SoC fabrics
  
  

Gen-Specific ExpectaƟons

• Gen5: 32 GT/s NRZ operaƟon, Ɵght Ɵming margins, EQ awareness
• Gen6: FLIT-mode architecture, PAM4 signaling, FEC/CRC, PHY latency budgeƟng
• Gen7/Gen8: Scalable RTL, reƟmer/chiplet awareness, reliability and RAS focus
  
  

Experience & QualificaƟons

• 8–12+ years of experience in high-speed interface RTL integraƟon
• Silicon-proven PCIe Gen5+ experience is mandatory
• Exposure to PCIe Gen6 FLIT-mode strongly preferred
• Experience with chiplet-based or mulƟ-die SoCs is a plus
  
  

Preferred DifferenƟators

• CXL 2.x / 3.x awareness
• ReƟmer/redriver integraƟon exposure
• Post-silicon debug and bring-up experience
• Security concepts (IDE, link-level protecƟon)