Job Title : RTL Design Engineer
Experience : 4-6 Years
Location : Bangalore
Job Description
We are looking for a strong RTL Design Engineer with hands-on experience in Verilog/System Verilog. This is a core RTL development role, owning block-level design from micro-architecture to high-quality, synthesizable RTL.
Key Responsibilities
- Own block-level RTL development from micro-architecture definition to clean, synthesizable RTL
- Strong RTL coding using Verilog/SystemVerilog (non-negotiable)
- Design and implement FSM/FSMD, apply pipelining, and optimize RTL for timing and performance
- Execute and close Lint, CDC, X-prop, and structural checks
- Debug RTL vs synthesis mismatches and functional issues
- Collaborate closely with Design Verification (DV) teams to resolve bugs efficiently
- Develop solid synthesis-friendly RTL with correct constraint intent at block/top level
- Support timing closure in collaboration with PD and STA teams
- Maintain clear and up-to-date RTL documentation, including design decisions and changes
Required Skills & Qualifications
- 4-6 years of hands-on experience in ASIC/SoC RTL design
- Excellent knowledge of Strong understanding of digital design fundamentals
- Experience with synthesis concepts and constraints
- Hands-on with Lint, CDC, and X-prop analysis tools
- Good debugging skills across RTL and synthesis stages
Good To Have
- Exposure to pipelined processor architectures (ARM or RISC-V preferred)
- Experience working in SoC environments with cross-functional teams
(ref:hirist.tech)
