- Lead and contribute to digital design of high-speed serial interface PHY IPs (USBx, PCIex, Ethernet, Display, HDMI)
- Define and enhance micro-architecture based on customer, analog, system, or interface layer requirements
- Implement RTL in Verilog, ensuring code quality with tools like Spyglass (Lint, CDC, RDC)
- Collaborate with verification teams to validate functionality and handle edge/corner cases
- Develop timing constraints and drive synthesis, DFT insertion, and timing closure with physical design teams
- Own blocks from specification through delivery with strong micro-architecture and RTL skills
The Impact You Will Have:
- Enhance performance and robustness of PHY IPs powering next-gen electronics
- Deliver innovative and high-quality digital designs that meet evolving industry needs
- Influence technology development at the intersection of digital and mixed-signal design
- Enable efficient collaboration across design, verification, and physical teams
- Support customer success with reliable and optimized IP solutions
- Strengthen Synopsys leadership in semiconductor IP through excellence in digital design
What You'll Need:
- 58 years of ASIC digital design experience
- Strong expertise in Verilog RTL and micro-architecture design
- Hands-on experience with timing constraints and synthesis flows
- Proficiency with Spyglass (Lint, CDC, RDC) or equivalent tools
- Scripting experience in TCL, PERL, or Python
- Strong debugging, analysis, and detail orientation
