RTL Design Engineer

Experience:

4+ years of experience in RTL design, SoC integration, and IP development with strong knowledge of design flows and verification methodologies.

Responsibilities:

• Perform integration of SoC and RTL coding for complex designs.
• Work on SoC flows includingSpyGlass-Lint, Synthesis (DC), and CDC checks.
• Develop andmaintainscripts for automation using Perl, Python, Shell, orTcl.
• Execute SoC integration tasks,SpyGlassLint, CDC, DC-Synthesis, and VCLP.
• Collaborate with cross-functional teams to ensure design quality and compliance.
• OptimizeRTL design for performance, power, and area.

Primary Skills:

• VHDL, Verilog, Micro-architecture, RTL coding.
• CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP.
• Scripting languages: Perl, Python, Shell,Tcl.

Secondary Skills:

• Synopsys/Cadence tool flow.
• ARM Cortex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, MIPI CSI/DSI, LPDDR.