Rtl Design

We are looking for an RTL Design Engineer & FPGA Validation Expert with 5+ years of experience.

Roles and Responsibilities

Collaborate with Architects and Understand feature requirements and contribute to Micro Architecture design decisions

Develop RTL from scratch and implementing new features based on architecture discussions and specifications

Guide and Lead verification, FPGA teams to ensure thorough validation of all implemented features and validate workflows.

Experience in SoC, ASIC IP Micro architecture design, RTL design, development, debug and Integration across multiple SoC, IP and Protocols.

Good at Silicon RTL Micro architecture design and development, understanding of full RTL to GDS flow.

Collaborate with verification, validation FW, SW teams to develop the feature.

Expertise in SoC debugging, solid experience in digital front end design for ASICs.

SW and HW debugging tools and utilities: VCS, ModelSim, shell/Python scripting, logic analyzer, PCIe analyzer.

Efficient, self-motivated and a quick learner.

Deep expertise in RTL design, microarchitecture, and FPGA validation, bring hands-on clarity to system-level design, SoC validation, and emulation workflows.

Technical Skills

HDL: Verilog HDL, VHDL

HVL: System Verilog

Scope of Verification: IP, SOC

Timing Closure/RTL Integration: STA, CDC, LINT, XDC

IP/Protocols Verified: Ethernet, AXI, AHB, APB, SPI, I2C, and UART.

Tools Expertise: Xilinx-Vivado, ModelSim, QuestaSim, and EDA-playground. Technical Skills

Expertise in RTL design and micro-architecture using Verilog/SystemVerilog.

Strong in digital design concepts, timing closure, low-power design, and SoC/ASIC integration.

Hands-on with EDA tools VCS, Spyglass, Design Compiler, PrimeTime, Verdi.

Knowledge of AMBA (AXI/AHB/APB) and high-speed interfaces (PCIe, DDR, USB, Ethernet).

Skilled in TCL/Python scripting and design automation flows.

Excellent debugging, teamwork, and mentoring skills.