RISC-V Design Verification Engineer

We're actively hiring a Senior Design Verification Engineer with strong hands-on experience in RISC-V CPU cores and cache subsystems for an immediate requirement.

Must-Have Skills

• Strong DV experience on RISC-V CPU cores (in-order / out-of-order)
• Solid understanding of RISC-V ISA & privilege architecture
• Hands-on verification of L1/L2 cache, coherency & memory ordering
• Expertise in SystemVerilog & UVM
• Excellent RTL & micro-architecture level debugging
  
  

Key Responsibilities

• Develop & maintain UVM-based verification environments
• Create directed & constrained-random tests for CPU and cache
• Verify pipeline, exceptions, interrupts, MMU & cache behavior
• Work closely with design and architecture teams
• Drive verification closure using coverage and quality metrics
  
  

Skills: rtl,dv,micro-architecture level debugging,risc-v cpu,design verification,design verification testing,universal verification methodology (uvm),systemverilog & uvm,cache