Bachelors or masters degree in electrical engineering or a related field, 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows,
Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler,
Exceptional knowledge of layout design methods, techniques, and methodologies, Experience with physical verification tools, such as Calibre or Assura,
Understanding of semiconductor process technologies and their impact on layout design,
Excellent problem-solving and systematic skills, Ability to work effectively in a team-oriented environment,
Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV), Good communication and interpersonal skills,
