Search by job, company or skills

S

R&D Engineering, Staff Engineer - IP Verification

7-12 Years
new job description bg glownew job description bg glownew job description bg svg
  • Posted 2 days ago
  • Be among the first 10 applicants
Early Applicant
Quick Apply

Job Description

  • Expertise in UVM and System Verilog.
  • Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage.
  • Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies.
  • Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol.

Job Responsibilities:

  • Able to contribute to the development of the VIP.
  • Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective.
  • Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology

More Info

Job Type:
Industry:
Employment Type:
Open to candidates from:
Indian

About Company

Job ID: 115962579

Similar Jobs