R&D Engineering, Sr Staff Engineer

• Designing and implementing self-checking test benches using modern verification techniques.
• Developing verification components such as bus functional models, monitors, and behavioral models.
• Implementing functional coverage and assertions using System Verilog.
• Creating and executing test and functional coverage plans based on device specifications.
• Analyzing and debugging simulation failures to identify root causes.
• Evaluating functional coverage results to ensure thorough verification.
• 
  

The Impact You Will Have:

• Ensuring the highest quality of IP verification, contributing to the reliability and performance of cutting-edge technology.
• Enhancing the efficiency of the verification process through innovative test bench designs.
• Contributing to the development of high-performance silicon chips that power a wide range of applications.
• Supporting the continuous improvement of verification methodologies and best practices.
• Collaborating with cross-functional teams to achieve project milestones and deliverables.
• Mentoring and guiding junior engineers, fostering a culture of knowledge sharing and continuous learning.
• 
  

What You'll Need:

• B.Tech/M.Tech with a minimum of 10+ years experience in IP verification.
• Proficiency in Verilog and System Verilog for test bench development.
• Experience with object-oriented verification languages like SV, UVM.
• Strong debugging skills and experience with industry-standard simulation tools such as Synopsys VCS, Verdi.
• Knowledge of FPGA architectures and experience in DDR IP verification.