Job Description:
As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :-
- Place and Route, CTS, Routablity analysis with respect to congestion.
- Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout)
- Integration of analog blocks, Meeting RC requirements for manual/special signals
- Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup.
- Responsible for all the integrity checks and post Tapeout eJob view release,
- Good scripting knowledge perl and TCL, familiar with caliber, Innovus,
- Understanding of VLSI fabrication process,
- Implementing timing ECOs. Implementing IR drop fixes, SPEF/GPD extraction, signal EM fixes, Noise analysis.
- Responsible for all the integrity checks and post Tapeout eJob view.
- Open to new responsibilities in context of rapid technological change.
- Good communication skills, work closely with the team members to accomplish PD milestone.
- Secondary competencies :- Good understanding of CTS, STA, PTSI and timing.
Relevant experience of CAD tools cadence Innovus, Calibre is preferred.
Experiance 4 to 8 years
R026551
