Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
- Develop on- and off-chip network microarchitectures for data and coherence transport that meet KPIs for next-generation SMP.
- Work closely with Cache/Nest PD architect to specify structures/topologies that are logically and physically realizable by the development team by the target tape-out date.
- Modify/develop cache coherence protocol that best supports coherence transport topology.
- Develop improvements to L2 and LLC micro architectures that improve KPIs.
- Work with core architects to develop improvements to L2-core interface and interactions that improves KPIs.
Required Technical And Professional Expertise
- Minimum 12 to 15 years of relevant experience with MS/PhD
- Hands-on RTL level experience of architecting and delivering Coherency features in processor
- Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP
- Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations
- Experience in working with Core architecture/ FW/ SW teams
- Exposure to System architecture
