Define and own process integration strategy for next-generation SiC and GaN power semiconductor technologies from technology development through high-volume manufacturing.
Architect and optimize complete semiconductor process flows in collaboration with external foundries and technology partners.
Lead process integration across epitaxy, implantation, oxidation, annealing, lithography, dielectric formation, etching, metallization, passivation, and backend process modules.
Define and execute comprehensive DOE strategies to establish robust process windows and improve manufacturability.
Establish process control methodologies, monitor critical process parameters, and improve process capability using statistical process control (SPC) techniques.
Correlate inline process data, electrical characterization, reliability results, and physical failure analysis to optimize process performance and manufacturing yield.
Lead yield improvement initiatives through defect reduction, process optimization, and systematic root-cause analysis.
Define process qualification strategy and ensure compliance with JEDEC, AEC-Q101, and customer-specific reliability requirements.
Lead technology transfer from development into high-volume manufacturing.
Provide technical leadership during foundry engagements, process audits, technology reviews, and manufacturing readiness assessments.
Develop long-term process technology roadmaps and evaluate emerging semiconductor process technologies.
Mentor engineers and provide technical leadership across cross-functional technology development programs.
Requirements
MS/PhD in Electrical Engineering, Materials Science, Semiconductor Physics, or a related discipline.
10+ years of experience in semiconductor process integration, technology development, or manufacturing engineering for power semiconductor devices.
Extensive experience with SiC, GaN, or advanced silicon power semiconductor technologies.
Deep understanding of semiconductor fabrication processes including epitaxy, ion implantation, oxidation, annealing, lithography, dielectric deposition, etching, metallization, passivation, and wafer processing.
Proven expertise in process integration, DOE, yield improvement, SPC, process capability analysis, and manufacturing process control.
Demonstrated experience working with external wafer foundries and technology partners in a fabless or hybrid manufacturing environment.
In-hand process development experience in a foundry environment is desirable.
Strong knowledge of semiconductor defect mechanisms, crystal defects, process variability, and reliability physics.
Experience correlating electrical characterization, inline metrology, and physical failure analysis for process optimization.
Thorough understanding of JEDEC, AEC-Q101, PPAP, and automotive quality requirements.
Demonstrated technical leadership, successful technology commercialization, and cross-functional project leadership.
Excellent communication, mentoring, and stakeholder management skills.
