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NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.
CTO/Frontend Innovation/NVM Design Technology Department is responsible for all embedded Non-Volatile Memory deployment across NXP business and product lines. Embedded NVM encompasses nearly all technology nodes and products which integrate Logic NVM, Flash or disruptive memory solutions (e.g. RRAM, MRAM). The implementation of Embedded NVM technologies that enhance application capabilities is a competitive advantage in the marketplace.
In this position, we are looking for Physical Design lead to join our NXP's NVM IP design group in Bangalore, India.
Are you ready to lead the Physical design competence and drive the implementation and sign-off of advanced MRAM/RRAM NVM IPs in FinFET technology nodes Can you develop efficient and automated implementation flows, and collaborate closely with the NVM design teams, NXP product development teams to deliver scalable, production‑ready NVM IP solutions across NXP's diverse product portfolio, including automotive
Scope of Responsibilities/Expectations
As the NVM IP Back‑End Design Lead for our newly formed Bangalore team, you will be part of a global NVM design organization. You will lead the back‑end design competence for a wide range of disruptive NVM IPs targeting Automotive MCUs, MPUs, and beyond. Your responsibilities will include:
Specific skills & knowledge
Job ID: 148914685
Skills:
static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis
Skills:
Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis
Skills:
Tcl, Verilog, Python, Perl, Clock Tree Synthesis, object-oriented programming, Place And Route, EDA Tools, floorplanning, VHDL, RTL-to-GDSII implementation, Synthesis, Timing Closure
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