Job Overview
As a Principal Front-End Engineer at Tevega Semi, you will lead the architecture, logic design, and front-end validation of complex Mixed-Signal IPs (e.g., ADCs, DACs, PLLs, SerDes). You will be responsible for defining the digital-analog interface, ensuring robust logic validation, and driving the methodology for multi-generational IP development.
Location: Bangalore
Experience: 15+ years
Key Responsibilities
- Technical Leadership & Architecture: Define and architect the digital control and logic interfaces for high-performance mixed-signal IPs from scratch.
- Logic Design & RTL Coding: Develop high-quality, synthesizable RTL for digital control logic, calibration algorithms, and power management blocks.
- Mixed-Signal Validation: Drive advanced validation strategies including AMS (Analog Mixed-Signal) simulations, co-simulation (e.g., Cadence Xcelium + Spectre), and behavioral modeling using Verilog-AMS, SystemVerilog (RNM), or Wreal.
- Design Convergence: Lead front-end implementation tasks including synthesis, Lint, CDC (Clock Domain Crossing) analysis, SDC validation, and power analysis.
- Cross-Functional Collaboration: Partner with Analog IC Design, Physical Design (PnR), and System Engineering teams to ensure seamless integration and timing/power closure.
- Post-Silicon Support: Drive silicon bring-up and debug to identify performance gaps and ensure final product-level specifications are met.
- Mentorship: Provide technical guidance to junior engineers and contribute to the company's long-term design methodology and IP roadmap.
Required Skills & Qualifications
- Education: BE/BTech/ME/MTech in Electrical/Electronics Engineering (Ph.D. preferred).
- Experience: 15+ years of experience in front-end design and validation of mixed-signal IPs or SoCs.
- Technical Expertise:
- Deep understanding of analog building blocks (ADCs, DACs, LDOs, PLLs) from a digital control perspective.
- Proficiency in SystemVerilog (UVM) for verification and Verilog-AMS for modeling.
- Expert knowledge of industry-standard EDA tools (Synopsys, Cadence, or Mentor) for front-end workflows.
- Familiarity with advanced FinFET technology nodes and sub-micron design challenges.
- Scripting: Strong skills in Python, Perl, Tcl, or Shell for automation and flow enhancement.
- Soft Skills: Exceptional problem-solving abilities and clear communication for multi-site development environments.
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