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Principal IP verification engineer

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  • Posted 21 hours ago
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Job Description

IP verification engineer - Principal

In this role you will be responsible for verifying complex IPs involving memory controllers, and interconnects, collaborating with global design and architecture teams.

Key Responsibilities

  • Develop and execute verification plans for memory controllers, interconnects and other infrastructural IPs
  • Build scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)
  • Own end-to-end IP verification sign-off
  • Achieve high-quality metrics including functional coverage and code coverage
  • Manage regressions and debug failures
  • Collaborate closely with design teams to resolve issues

Required Expertise

Experience: 10+ years

  • Strong experience in SystemVerilog, UVM, and Verilog
  • Good understanding of Functional verification methodologies, Assertions (SVA) and coverage
  • Good understanding of interconnect protocols such as AXI, AHB, CHI and PCIE
  • Experience debugging complex RTL and testbench issues
  • Experience in Formal verification is an added plus

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Job ID: 149386229

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Bengaluru, India

Skills:

code coverage CShellPerlVerilogDebuggingPythonSystem VerilogTclUVM methodologyMetric Driven Verificationformal verification methodologiesassertionsfunctional coverageconstrained random methodologies