Principal Engineer Infrastructure Package & timing

In your new role you will:

• Define and create padframe /pinning concept for microcontroller products within a team.
• Set targets for timing sign off and support integration teams to achieve timing closure
• Develop Clock reset concepts and transfer the concepts to implementable solutions
• Ensure that packaging aspects are comprehensively considered in thewhole development process
• Perform quality checks with respective status assessment andreporting using tools like simulators or code checkers.
• Development of new methodologies, service/debugging/bug fixing of existing tools and software.

You are best equipped for this task if you have:

• A degree in electrical / electronic /communications engineering, computer science, physics or a related technical field
• Extensive knowledge in Digital Implementation flows Soc integration preferred
• Broad knowledge of SoC architecture development needed (incl.Clk/reset concepts, padframe/pinning, timing closure and packaging)
• Detailed knowledge about sub-micron CMOS technologies and experiencein FinFET technologies is a plus
• Excellent communication and coordination skills in English.
• The candidate should be able to work independently, but also beteam-oriented and open to innovative approaches and methods in avolatile environment