Principal Design Engineer

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Job Description

Location:

Position is based in Bangalore.

Job Description:

We are looking for strong technical team lead for IP Integration, subsystem creation, and QA for our SSG IP Integration and QA engineeringteam. The role would include working with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features. In addition, responsibilities include ensuring various customer configurations are clean as part of verification regressions, and ensuring design is clean for all QA aspects in both Front End and Back End (these includes items like being Timing/LINT/RDC/CDC clean, consistency checks for all IP views etc. A critical part of this role is for the technical lead to also oversee the adoption and roll out of Agentic AI initiativesinto all aspects of IP Integration and QA including multi-agent connections in CDNS EDA flows. They will work closely with various RnD IP leaders and Central Engineering teams around the world to ensure integration and release of IPs are handled on time and with Quality. The lead should also be able to identify constant process improvement and automation to increase the efficiency of the entire RnD IP release process. The role will include people management, and the lead would be responsible for technical and personal growth of their team. This is a highly visible role as it is serves as a critical final touchpoint from RnD to Customers and our IP teams success hinges on the efficiency and throughput of this team.

Requirements:

.Education:

Exp: 8-15 years or Equivalent or Relavent

oCollege education in Electronics Engineering or Computer Engineering

.Experience/Abilities:

oCandidate should be proficient in ASIC development flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint, CDC, LEC etc.

oFamiliarity with Power Flow (UPF/CPF).

oExperience with functional simulation using Verilog/System Verilog and ability to debug existing Verilog/System Verilog test cases with little or no help from the designer

oGood in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency.

oBug reporting and resolution closure with IP providers

oAbility to debug synthesis/timing analysis constraints, reports, logs

oAbility to learn new tools/flows and develop methodology if needed.

o8+ years of relevant experience in Digital Design and verification.

.Soft Skills:

oAbility to build and maintain close relationships with all stake holders such as RnD, Application/Product Engineers, Program Managers, Sales, etc

oStrong communication skills, both oral and written

oNeed to be results and data driven while being able to pay attention to details

oGood time management skills to balance multiple high-priority projects.

oAbility to efficiently lead and train teams

oFastidious approach to building automated processes.

oStrong interpersonal and relationship-building skills.

oPassionate about quality and ensuring our customer have the best experience

.Additional Desirable Qualifications:

oFamiliarity with UCIE(Die-to-Die) Design-IP's & Analog design flows

oFamiliarity with IP release and tracking management systems

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