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Cadence Design Systems

Principal Design Engineer

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Job Description

  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • 8+ years of Design Verification experience with SV/UVM
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.

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Open to candidates from:
Indian

About Company

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. For six years in a row, Fortune Magazine has named Cadence one of the 100 Best Companies to Work For. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health. We pride ourselves on creating and sustaining a company culture, that drives innovation and business success. Cadence is recognized as a Great Place to Work around the world, including as one of the Fortune “100 Best Companies to Work For” over the last six years.

Job ID: 117751753

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