Unix Shell, System Verilog, Perl, Automated flows, Uvm, Gate Level Simulations, formal verification, Design Verification, NoCs, Interconnects

Unix Shell, System Verilog, Perl, Uvm, Gate Level Simulations, formal verification, NoCs, Design Verification, Automated flows, Interconnects

regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Static Timing Analysis, Python, Logic Design, Jasper, Perl, Tcl, Sta, IR drop, RTL implementation, post silicon validation, DFT concepts, Cadence Modus, Verification, Synthesis, ATPG tools, coverage analysis, Scan Insertion, RTL2GDS flow, Logic Synthesis, debugging skills, RTL lint tools, ATE debug, Logic Equivalent Checking, EDA Tools

Area, PPA Performance, Micro-architecture, Timing, LPDDR6, Rtl Design, JEDEC specifications, DDR Controller

Jtag, System Verilog, Static timing analysis, DFT techniques, IEEE 1500 Standard, Commercial test generation tools, Logic diagnosis, Yield learning, Synopsys DFT Max, Tetramax tools, Verification UVM methodology, Mentor Tessent, IEEE 1687 standard, ATPG test pattern translation, ATPG tools, Scan insertion tools, Chip design Verilog, MBIST, Familiarity with ATE, Scripting Perl, Scan compression, Test compression software, Gate-level simulations, LBIST