constraint analysis , DDR, Perl, Verilog, System Verilog, Tcl, Sta, Synthesis, Debug, Simulation, DRAM protocol, GDDR, timing constraints generation, high-speed PHYs, design for test, formal verification, LINT, Timing Closure, Design Methodologies, functional coverage

Verilog, System Verilog, LPDDR, Uvm, DDR memory protocols, HBM, Functional Verification

Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES