Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs.
Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets.
Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance.
Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems.
Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools.
Supervise physical layout to minimize parasitics, device stress, and process variation impacts.
Review simulation and measurement data for design validation and compliance with PCIe standards.
Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices.
Document design features, specifications, test plans, and methodologies for future reference.
Collaborate with the characterization team to validate the electrical performance of circuits in silicon.
The Impact You Will Have:Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology.
Ensure that Synopsys analog/mixed-signal circuits meet stringent industry standards, enhancing the companys reputation for excellence.
Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance.
Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team.
Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability.
Enhance the companys design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits.
What You ll Need:PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs.
Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs.
Proven silicon experience in developing PHY circuits that meet strict PCIe standards.
Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design.
Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis).
Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity.
Extensive experience with the porting of PHY designs across different technology nodes.
Strong expertise in CMOS technologies, including finFET and SOI processes.
In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking.
Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration.
Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes
