Power Management Design Architect (PMU/PMIC)

Power Management Design Architect (PMU/PMIC)

Location: Noida, Indi

aWork Mode: Onsit

eExperience: 5–15 Year

• s
  Role Overvi

ew
We are looking for a Power Management Design Architect to lead the architecture, design, and validation of PMU/PMIC solutions. The role involves end-to-end ownership from concept to silicon validation. The candidate will work on DC-DC converters, LDOs, and key analog building blocks for power-efficient semiconductor syste

• ms.
  Key Responsibili
• tiesDefine and develop end-to-end PMU/PMIC architec
• tureDesign DC-DC converters (Buck/Boost) and LDO regula
• torsArchitect and design key analog blocks such as bandgap reference, error amplifier, and gate dri
• versDevelop and optimize control loops, compensation, and stabi
• lityDrive power efficiency, transient response, and low quiescent current perform
• anceEnsure design robustness across PVT (Process, Voltage, Temperature) variat
• ionsPerform simulations, design verification, and corner anal
• ysisLead silicon bring-up, debugging, and characterization activi
• tiesAnalyze lab data and correlate with simulation res
• ultsCollaborate with layout, digital, and system teams for design integra
• tionMentor junior engineers and provide technical guid
• anceSupport product-level validation and documenta

• tion
  Required Qualifica
• tionsM.Tech or PhD in Electronics / Electrical Engineering or related
• field5–10 years of experience in Analog / Power IC D
• esignProven track record of successful silicon in PMIC or DC-DC de
• signsStrong fundamentals in analog and power electronics d
• esignTechnical Skills (Grouped & Struct

ured)
Power Management

• DesignPMU / PMIC architecture
• designDC-DC converters (Buck /
• Boost)Low Dropout Regulators

(LDOs)
Analog Circuit

• DesignBandgap reference
• designError amplifier
• designGate driver c
• ircuitsCompensation and control loop

design
Performance Opti

• mizationStability analysis and loop comp
• ensationPower efficiency opti
• mizationTransient respons
• e tuningLow-power / low quiescent curren

t design
Process & V

• alidationPVT analysis (Process, Voltage, Tem
• perature)Silicon bring-up and lab v
• alidationDebugging and charact

erization
Tools &

• SimulationCadenc
• e Virtu
• osoSpe

ctreMATLAB
Technolo

• gy ExposureCMOS / BCD process t
• echnologiesGood to Have
• (Optional)Experience in automotive or low-power a
• pplicationsExposure to system-level power
• managementKnowledge of EMI/EMC considerations in p
• ower designExperience working across multiple techn

ology n