About the Company: We are seeking a highly experienced Power-Management & PLL Circuit Engineer to lead the design and development of advanced power-management circuits and PLL IPs for complex SoCs. This is a senior, hands-on technical role requiring deep analog/mixed-signal expertise.
About the Role: A short paragraph summarizing the key role responsibilities.
Responsibilities:
- Lead the design of power-management circuits: LDOs (ultra-low noise, capless, fast-transient), DC-DC converters (PWM/PFM), and voltage regulators.
- Design and implement high-performance PLL circuits for frequency synthesis and clock generation.
- Perform advanced transistor-level simulations, modeling, and analysis to ensure performance and robustness.
- Work closely with layout teams to guide floorplanning, layout practices, and physical design reviews.
- Drive lab bring-up, silicon debug, and characterization of PMIC and PLL circuits.
- Define specifications and system-level requirements in collaboration with architecture and SoC teams.
- Mentor and guide junior engineers in circuit design, simulation, and lab methodologies.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering or related field.
- 10+ years of hands-on experience in power-management and PLL circuit design.
Required Skills:
- Strong foundation in analog/mixed-signal fundamentals and feedback loop stability.
- Expertise in designing LDOs, DC-DC converters, voltage regulators, and PLL building blocks.
- Proficiency with industry-standard simulation tools (Cadence Virtuoso, Spectre, ADE, etc.).
- Strong experience with lab testing, silicon validation, and characterization equipment.
Preferred Skills:
- Additional relevant experience or certifications.
Pay range and compensation package: Pay range or salary or compensation.
Equal Opportunity Statement: Include a statement on commitment to diversity and inclusivity.
