PLL Design Architect
- Location, Work Mode, Experience RangeLocation: Noida, India
- Work Mode: Onsite
- Experience: 8–15 Years
- Role Overview
We are looking for an experienced PLL Design Architect to lead the architecture and design of high-performance Phase-Locked Loop (PLL) systems for advanced semiconductor applications. The role involves defining system-level specifications, driving circuit-level implementation, and ensuring robust silicon performance across process, voltage, and temperature (PVT) conditions
- .Key Responsibilitie
- sDefine and develop PLL architectures including Integer-N, Fractional-N, ADPLL, and LC PL
- LDesign and optimize critical PLL building blocks such as PFD, Charge Pump, Loop Filter, VCO, and Frequency Divider
- sPerform detailed analysis of phase noise, jitter, loop stability, and frequency synthesis performanc
- eDrive architecture trade-offs for power, performance, and area (PPA) optimizatio
- nEnsure robust design across PVT corners with parasitic-aware simulation
- sPerform system-level modeling and verification using MATLAB or equivalent tool
- sCollaborate with layout teams for analog layout reviews and parasitic extraction consideration
- sLead silicon bring-up, debugging, and characterization activitie
- sAnalyze silicon results and correlate with pre-silicon simulation
- sWork closely with digital, mixed-signal, and system teams for integratio
- nMentor junior engineers and provide technical guidanc
- eParticipate in design reviews and documentation of architecture and design decision
- sRequired Qualification
- sB.Tech / M.Tech / PhD in Electronics, Electrical Engineering, or related fiel
- d8+ years of experience in Analog / RF IC design with strong PLL design exposur
- eProven track record of successful silicon tape-out
- sStrong understanding of PLL system architecture and circuit desig
- nTechnical Skill
sPLL & Analog Desig
- nPhase-Locked Loop (PLL) design and architectur
- eLoop dynamics, stability, phase noise, and jitter analysi
- sInteger-N, Fractional-N, ADPLL, LC PL
LCircuit Design Expertis
- ePhase Frequency Detector (PFD
- )Charge Pump desig
- nVoltage Controlled Oscillator (VCO
- )Loop Filter desig
- nHigh-speed frequency divider
sTools & Simulatio
- nCadence Virtuos
- oSpectre / SpectreR
- FMATLAB / System modeling tool
sProcess & Silico
- nCMOS technology nodes (advanced nodes preferred
- )Parasitic extraction and post-layout simulation
- sSilicon bring-up and validatio
- nGood to Have (Optional
- )Experience with RF transceiver or clocking subsystem
- sKnowledge of high-speed SerDes clocking architecture
- sExposure to low-power or high-frequency PLL desig
- nExperience with scripting (Python/MATLAB automation
- )Prior experience in leading small design team
s#LI-VA
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