Job Description: Physical Design Lead Engineer
Role Summary
We are seeking a highly skilled
Physical Design Lead Engineer to spearhead the physical implementation of our next-generation ASIC and SoC projects. You will be responsible for the entire journey from RTL handoff to GDSII delivery, ensuring that our designs meet stringent performance, power, and area (PPA) targets while adhering to foundry-specific requirements. As a lead, you will manage complex technical workflows and provide mentorship to junior engineers to ensure project success.
Key Responsibilities
Execution & Technical Leadership
- Full Flow Ownership: Lead and execute comprehensive physical design activities for ASIC/SoC projects, managing the complete flow from RTL to GDSII.
- Implementation Core: Drive critical phases of the design cycle, including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
- Optimization: Continuously optimize designs for PPA while ensuring full compliance with all foundry requirements.
- Post-Layout Operations: Handle ECO (Engineering Change Order) implementations and oversee post-layout simulations to validate design integrity.
Analysis & Sign-off
- Reliability Checks: Perform detailed power analysis, IR drop evaluations, and electromigration (EM) checks to ensure silicon reliability.
- Physical Verification: Manage the physical verification process, including DRC (Design Rule Check) and LVS (Layout vs. Schematic), through to final sign-off.
Collaboration & Mentorship
- Cross-Functional Synergy: Collaborate closely with RTL, synthesis, and verification teams to identify and resolve complex design issues.
- Team Development: Actively mentor and guide junior physical design engineers to foster technical growth within the team.
- Vendor Relations: Coordinate with EDA vendors to stay updated on the latest tools, methodologies, and technological advancements.
Required Qualifications
- Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Technical Expertise: Proven track record in physical design for advanced process nodes (e.g., 7nm, 5nm, or below).
- Tool Proficiency: Expertise in industry-standard EDA tools (e.g., Innovus, IC Compiler II, Primetime, Calibre).
- Leadership: Strong leadership and communication skills with experience managing technical project timelines.
