About the team: You will join a dynamic, global team of experts dedicated to advancing the state-of-the-art in high-performance cores and IP implementation. The team is at the forefront of developing innovative methodologies and leveraging Synopsys industry-leading tools to solve the most critical design challenges in semiconductor technology.
Job Description
- Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.
- Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.
- Drive flow development and optimization to improve design quality and predictability.
- Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).
- Contribute to the adoption and integration of advanced technologies and tool features in design implementation.
- Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.
- Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.
- Participate in technical reviews and provide guidance on best practices for low-power, high-performance design.
Skills & Experience
- Minimum 5 years of experience in physical design, with a focus on high-performance and low-power methodologies.
- Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.
- Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.
- Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.
- Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.
- Bachelor's or Master's degree in Electrical Engineering or related field.
